1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and particularly to a random access memory provided with memory cells having MTJs (Magnetic Tunnel Junctions).
2. Description of the Background Art
Attention is being given to an MRAM (Magnetic Random Memory) device as a memory device, which can nonvolatilely store data with low power consumption. The MRAM device is a memory device, in which a plurality of thin film magnetic members are formed in a semiconductor integrated circuit for nonvolatilely storing data, and random access to each thin film magnetic member is allowed.
Particularly, in recent years, it has been announced that a performance of the MRAM device can be dramatically improved by using the thin film magnetic members, which utilize the magnetic tunnel junctions, as memory cells. The MRAM device with memory cells having the magnetic tunnel junctions has been disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000 and xe2x80x9cNonvolatile RAM Based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 22 conceptually shows a structure of a memory cell, which has a tunnel junction, and may be merely referred to as a xe2x80x9cMTJ memory cellxe2x80x9d hereinafter.
Referring to FIG. 22, an MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance, which is variable in accordance with a data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is located between a bit line BL and a ground voltage line GL, and is connected in series to tunneling magneto-resistance element TMR. Typically, access transistor ATR is formed of a field-effect transistor.
For the MTJ memory cell, the device includes bit line BL for carrying a data write current and a data read current in a data write operation and a data read operation, respectively, a write digit line WDL for carrying the data write current in the data write operation, a word line WL for instructing data reading, and ground voltage line GL for puling down tunneling magneto-resistance element TMR to a ground voltage GND in the data read operation.
In the data read operation, tunneling magneto-resistance element TMR is electrically coupled between ground voltage line GL carrying ground voltage GND and bit line BL in response to turn-on of access transistor ATR.
FIG. 23 conceptually shows an operation of writing data in the MTJ memory cell.
Referring to FIG. 23, tunneling magneto-resistance element TMR has a magnetic material layer FL, which has a fixed magnetization direction, and may be merely referred to as a xe2x80x9cfixed magnetic layerxe2x80x9d hereinafter, and a magnetic material layer VL, which is magnetized in a direction depending on a data write magnetic field caused by the data write current, and may be merely referred to as a xe2x80x9cfree magnetic layerxe2x80x9d hereinafter. A tunneling barrier TB formed of an insulator film is disposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction in accordance with the level of the storage data to be written.
Tunneling magneto-resistance element TMR has an electric resistance, which is variable depending on a correlation in magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, when fixed and free magnetic layers FL and VL are magnetized in the same direction, the electric resistance is smaller than that in the case where these are magnetized in the opposite directions.
In the data write operation, word line WL is inactive, and access transistor ATR is off. In this state, the data write currents for magnetizing free magnetic layer VL are supplied to bit line BL and write digit line WDL in directions depending on the level of write data, respectively. Thus, the magnetization direction of free magnetic layer VL depends on the directions of data write currents flowing through bit line BL and write digit line WDL, respectively.
FIG. 24 conceptually illustrates a relationship between the data write current and the magnetization of the free magnetic layer VL.
Referring to FIG. 24, an abscissa H(EA) gives a magnetic field, which is applied in a direction of an easy axis (EA) to free magnetic layer VL of tunneling magneto-resistance element TMR. An ordinate H(HA) indicates a magnetic field acting in a direction of a hard axis (HA) on free magnetic layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields produced by currents flowing through bit line BL and write digit line WDL, respectively.
In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is parallel to the easy axis of free magnetic layer VL, and free magnetic layer VL is magnetized in the direction along the easy axis, and particularly in the same parallel direction, which is the same direction as fixed magnetic layer FL, or in the opposite-parallel direction, which is opposite to the above direction, depending on the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the storage data. The MTJ memory cell can selectively store data (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of one bit depending on the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL can be rewritten only when a sum of applied magnetic fields H(EA) and H(HA) falls within a region outside an asteroid characteristic line illustrated in FIG. 24. Therefore, the magnetization direction of free magnetic layer VL does not switch when the data write magnetic fields applied thereto have intensities corresponding to a region inside the asteroid characteristic line.
As can be seen from the asteroid characteristic line, the magnetization threshold required for switching the magnetization direction along the easy axis can be lowered by applying the magnetic field in the direction of the hard axis to free magnetic layer VL.
For rewriting the storage data of the MTJ memory cell, i.e., the magnetization direction of tunneling magneto-resistance element TMR, it is necessary to pass the data write currents at a predetermined level or higher through write digit line WDL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the same direction as fixed magnetic layer FL or the opposite (opposite-parallel) direction depending on the direction of the data write magnetic field along the easy axis (EA). The magnetization direction, which was once written into tunneling magneto-resistance element TMR, and thus the storage data of MTJ memory cell is held nonvolatilely until next data writing is executed.
FIG. 25 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 25, access transistor ATR is turned on in response to activation of word line WL in the data read operation. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line BL while being pulled down with ground voltage GND.
In this state, bit line BL is pulled up with a predetermined voltage, whereby a current path including bit line BL and tunneling magneto-resistance element TMR carries a memory cell current Icell corresponding to the electric resistance of tunneling magneto-resistance element TMR, and thus to the storage data of the MTJ memory cell. For example, this memory cell current Icell is compared with a predetermined reference current, whereby storage data can be read out from the MTJ memory cell.
As described above, the electric resistance of tunneling magneto-resistance element TMR changes in accordance with the magnetization direction, which is rewritable by the data write magnetic field applied thereto. Therefore, nonvolatile data storage can be executed by establishing a correlation of electric resistances Rmax and Rmin of tunneling magneto-resistance element TMR with respect to levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of the storage data.
In the data read operation, a data read current Is flows through magnetic tunneling junction MTJ. However, data read current Is is generally determined to be smaller by one or two digits than the data write current already described. This reduces a possibility that the storage data of the MTJ memory cell is erroneously rewritten due to data read current Is in the data read operation.
FIG. 26 is shows a structure of the MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 26, access transistor ATR formed on a semiconductor substrate SUB has source/drain regions 310 and 320 formed of n-type regions as well as a gate region 330. Source/drain region 310 is electrically coupled to ground voltage line GL via a metal film formed in a contact hole 341.
Write digit line WDL is formed in a metal interconnection layer arranged at a higher level than ground voltage line GL. Tunneling magneto-resistance element TMR is arranged at a higher level than write digit line WDL. Tunneling magneto-resistance element TMR is electrically coupled to source/drain region 320 of access transistor ATR via a strap SL and a metal film formed in contact hole 340. Strap SL is provided for electrically coupling tunneling magneto-resistance element TMR to access transistor ATR, and is made of an electrically conductive material.
Bit line BL is electrically coupled to tunneling magneto-resistance element TMR, and is arranged at a higher level than tunneling magneto-resistance element TMR. As already described, the data write currents must flow through both bit line BL and write digit line WDL in the data write operation. In the data read operation, word line WL is activated to attain, e.g., a high voltage level so that access transistor ATR is turned on. Thereby, tunneling magneto-resistance element TMR is pulled down via access transistor ATR to ground voltage GND, and is electrically coupled to bit line BL.
Bit line BL carrying the data write current and data read current as well as write digit line WDL carrying the data write current are made of metal interconnection layers. Word line WL is provided for controlling the gate voltage of access transistor ATR, and is not required to carry positively or actively a current. For increasing a degree of integration or a density, therefore, an independent metal interconnection layer dedicated to word line WL is not generally employed, and word line WL is generally formed at the same interconnection layer as gate 330 by using a polycrystalline silicon layer or a polycide layer.
However, as shown in FIG. 26, strap SL and contact hole 340, which electrically couple tunneling magneto-resistance element TMR and access transistor ATR, are employed for reading data from the MTJ memory cell, and these strap SL and contact hole 340 must be arranged to avoid write digit line WDL. Accordingly, the MRAM device provided with the plurality of MTJ memory cells in an integrated fashion cannot have a sufficiently high element density due to layout restrictions, and an array area thereof becomes large.
An object of the invention is to provide a thin film magnetic memory device, which allows reduction in area of a memory array provided with MTJ memory cells in an integrated fashion.
In summary, the invention provides a thin film magnetic memory device including a plurality of memory cells, a plurality of first signal lines and a plurality of second signal lines. The plurality of memory cells are arranged in rows and columns, and are divided into a plurality of row blocks each extending in a row direction. Each of the memory cells includes a tunneling magneto-resistance element having an electric resistance variable depending on magnetically written storage data. The plurality of first signal lines are arranged in a column direction, and correspond to the memory cell columns, respectively. The plurality of second signal lines are arranged corresponding to the plurality of row blocks in each of the memory cell columns, respectively. The tunneling magneto-resistance element is electrically coupled between corresponding one of the plurality of first signal lines and corresponding one of the plurality of second signal lines.
Accordingly, the invention has a major advantage that the contact hole, which is conventionally provided under severe layout constraints for electrically coupling the memory cell and another element such as an access transistor, can be arranged only for each second signal line and not for each memory cell. Consequently, an area of a memory array can be reduced.
Preferably, the thin film magnetic memory device includes a plurality of word lines and a plurality of access transistors. The plurality of word lines are arranged in the row direction, correspond to the plurality of row bocks, respectively, and are selectively activated in accordance with results of row selection in a data read operation. The plurality of access transistors are arranged corresponding to the plurality of second signal lines, respectively. Each of the access transistors is electrically coupled between corresponding one of the plurality of second signal lines and a fixed voltage, and is turned on when corresponding one of the word lines is activated.
Since each access transistor can be shared by the plurality of memory cells, it is possible to reduce the number of the required access transistors. Accordingly, the area of the memory array can be further reduced.
Preferably, each of the row blocks has the memory cell rows of L (L: integer larger than one) in number, and the second signal line corresponding to the selected memory cell being selected as an access target is coupled to a first voltage over at least one predetermined period provided during a single data read operation. The thin film magnetic memory device further includes a data line to be electrically coupled to the first signal line corresponding to the selected memory cell during each of the at least one predetermined period, a read current supply circuit for coupling the data line to a second voltage during each of the at least one predetermined period, and a data read circuit for producing read data corresponding to the storage data of the selected memory cell. The data read circuit has a first voltage holding portion for holding, on a first internal node, the voltage carried on the data line over the predetermined period provided corresponding to a first state keeping the selected memory cell to have a magnetization direction substantially same to that before the single data read operation, and a voltage comparing portion for producing the read data in accordance with a difference between the voltage on the first internal node and the voltage carried on the data line over the predetermined period provided corresponding to a second state changing the magnetization direction of the selected memory cell from that in the first state by application of a predetermined magnetic field.
Thereby, the storage data can be extracted from the one selected memory cell among the memory cells of L in number connected to the same second signal line by accessing the memory cells of L in number. Further, the data reading can be executed in the self-reference manner not using a reference cell, and therefore can be executed based on a comparison between voltages obtained via the same data read path including the same memory cell group, data line and others. Accordingly, it is possible to avoid influences by offset and others due to variations in manufacturing of respective circuits forming the data read path, and the data read operation can be performed precisely.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.